FPGA Accelerated Secure Data Communication
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Authors
AlBader, Sadoon
Dhari SlMejren
Ibrahim Al-Shammari
Bader Al- Failakawy
Issue Date
2021-01-31
Type
Language
Keywords
CPEG
Alternative Title
Abstract
Many methods of encryption and authentication have been used in communications and many vulnerabilities have been found in them, prompting researchers to explore new algorithms for unbreakable security and privacy codes. Moreover, most of the recent sophisticated algorithms suffer from the mathematical complexity that requires many CPU cycles to be used for encryption, decryption, and authentication. In addition, implementing hardware accelerated security algorithms is dangerous, due to its sensitivity to flaws in the algorithms.
This CDP explores feasible solutions to this problem by allowing communication devices to use configurable hardware, such as FPGAs, while offloading CPU resources, to implement security tasks, while also enabling a possibility of reprogramming when a vulnerability is found in an algorithm, much like a simple replacement of a device within a computer but done automatically through a software update.
One vendor that manufactures open-source computer mainboard designs using IBM’s OpenPOWER architecture, has used an FPGA to control many of the board’s features, allowing the FPGA to be updated for security, bug fixes, as well as new features, something that was impossible on non-programmable hardware. This motivated us to explore using open-source implementation of poly1305+Salsa20, translating an available implementation from VHDL to SystemVerilog, and porting it from a Xilinx board to a more universal implementation (due to regional unavailability of Xilinx software), writing a full Linux kernel driver for the new device, and demonstrating the throughput advantage of the FPGA when compared to many computers that will be tested.
Description
Citation
Publisher
College of Engineering and Applied Sciences