Co-designs of Parallel Rijndael, The International Symposium on System-on-Chip
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State-of-the-art Field Programmable Gate Arrays (FPGAs) have inspired the innovation of hardware/software co-design methodologies that provide a high-level of abstraction in the design process. In this paper, we explore the effectiveness of a formal methodology in the co-design of parallel versions of the Rijndael cryptographic algorithm. The investigated methodology employs the functional paradigm for specifications, derived concurrency, and hardware mapping. Several implementations are developed with different performance characteristics. The refined designs are tested under RC-1000 reconfigurable computer with its two million gates FPGA.