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dc.contributor.authorEL Abd. Mohammed
dc.contributor.authorDamaj, Issam
dc.date.accessioned2021-01-18T07:22:49Z
dc.date.available2021-01-18T07:22:49Z
dc.date.issued1/4/2020
dc.identifier.urihttps://www.sciencedirect.com/science/article/abs/pii/S0141933119303448
dc.identifier.urihttps://dspace.auk.edu.kw/handle/11675/6666
dc.description.abstractBrain Storm Optimization (BSO) is a metaheuristic algorithm that has been gaining attention in solving engineering problems. The algorithm emulates the human brainstorming procedure by initializing a population and optimizing it over several generations. The algorithm enjoys intrinsic parallelism that enables the development of high-speed hardware implementations. However, investigations on accelerating the BSO are yet limited in the literature. In this paper, we present a parallel BSO processor under Field Programmable Gate Arrays (FPGAs). The development includes sequentially modeling the algorithm, deriving parallel versions, targeting a rich set of benchmark evaluation functions, and performing thorough validations. The results confirm the achievement of appealing performance characteristics that significantly outperform software implementations in terms of execution speed. The paper includes thorough analysis, evaluation, and sets the ground for future works.
dc.publisherMicroprocessors and Microsystems
dc.relation.journalMicroprocessors and Microsystems
dc.titleParallel hardware implementation of the brain storm optimization algorithm using FPGAs
dc.typeJournal Article
dcterms.bibliographicCitationHassanein, A., El-Abd, M., Damaj, I., & Ur Rehman, H. (2020). Parallel hardware implementation of the brain storm optimization algorithm using FPGAs. Microprocessors and Microsystems, 74, 103005. https://doi.org/https://doi.org/10.1016/j.micpro.2020.103005


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